High Speed and Low Power Pipelined ADC Design for MRI Application
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The advancement in the integrated circuit technologies has led to the development of many high speed devices. This lead to the necessity to have a fast and efficient circuit which can provide high computational capability. One such device is an Analog to Digital Converter (ADC). The ADC is one of the most basic components of the any digital or analog circuit when there is an interfacing between the digital system and the real-world which is analog in nature. So this forms a primary and an essential block of a computing digital system. The advancement in the Integrated Circuit (IC) industries has led to the growth in the Medical industries. One such development is the advance magnetic resonant scanners in the market. The Magnetic Resonant Imaging (MRI) is a popular imaging technique over Computed Tomography (CT). The signals captured by the MRI machine is an analog signal which has to be processed by the digital processor. So the MRI machines need to have a faster and high resolution ADC. Since the images captured by the scanner has to be processed for high clarity, the resolution has to be very high. The thesis project focus on designing a high speed Pipelined ADC for MRI applications. A complementary CMOS based 9 bit Pipelined ADC is proposed in this thesis which converts the analog waves into a digital word with minimum number of comparators and thereby increasing the speed and reducing the power of the device. The ADC consist of three stages. Each stage is built using a high speed 3 Bit Flash ADC. The ADC has a high sampling rate up to 5GHz and high resolution of 9 bits. The Direct Current (DC) analysis of the design shows that the design consumes 450mW of power. The layout for the design is implemented with IBM 180nm CMOS technology which consumes an area of 9.24mm² .
Table of Contents
Introduction -- Overview of ADCs -- ADC design for magnetic resonant imaging -- Design to flash ADC -- Design of pipelined ADC -- Conclusion
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M.S.