Department of Computer Science and Electrical Engineering (UMKC)
https://hdl.handle.net/10355/8002
The Department of Computer Science and Electrical Engineering is a department in the UMKC School of Computing and Engineering.2024-03-28T17:33:06Z3D Hand Pose Estimation Via a Lightweight Deep Learning Model
https://hdl.handle.net/10355/65996
3D Hand Pose Estimation Via a Lightweight Deep Learning Model
Suggala, Prudhvi Sai
Deep Learning with depth cameras has enabled 3D hand pose estimation from RGBD
images. Commercial solutions like Leap Motion and Intel RealSense™ use stereoscopic sensors or
IR illumination-based methods to capture the depth in a photograph and further estimate pose
using Deep Learning (DL) methods. These hand pose estimation work has not considered the use
of virtual reality (VR) apps on mobile devices because this requires extensive computational
resources including hardware for processing the acquired depth. Previous works in 3D hand pose
estimation are based on the large pre-trained DL models in the pose estimation pipeline which
are not suitable to run on mobile devices.
In this work, we address the problem of hand pose estimation from monocular RGB
images (instead of RGBD images) and making DL models suitable to run on mobile VR. This task
is so challenging due to the missing depth information, we propose a deep neural network (DNN)
that learns a 3D hand articulated prior to estimating the 3D pose from RGB images. Our approach
comprises of (1) Localization network predicts the location of hands in the image, (2) sparse
adversarial auto-encoders trained on hand RGB images, and (3) adversarial auto-encoder for
capturing 3D hand pose distributions.
Finally, the proposed model yielded the accuracy comparable to state-of-the-art 3D hand
pose estimation. However, our model is much smaller than the existing models so that we
significantly accelerated the model execution and greatly reduced the run-time 2.6X faster than
the current solutions.
Title from PDF of title page, viewed September 28, 2018; Thesis advisor: Yugyung Lee; Vita; Includes bibliographical references (pages 32-33); Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2018
2018-01-01T00:00:00Z3D modeling and integration of current and future interconnect technologies
https://hdl.handle.net/10355/84403
3D modeling and integration of current and future interconnect technologies
Yousuf, Abdul Hamid Bin
To ensure maximum circuit reliability it is very important to estimate the circuit
performance and signal integrity in the circuit design phase. A full phase simulation for
performance estimation of a large-scale circuit not only require a massive computational
resource but also need a lot of time to produce acceptable results. The estimation of
performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect
capacitance. So, an accurate model for interconnect capacitance can be used in the circuit
CAD (computer-aided design) tools for circuit performance estimation before circuit
fabrication which reduces the computational resource requirement as well as the time
constraints. We propose a new capacitance models for interconnect lines in multilevel
interconnect structures by geometrically modeling the electrical flux lines of the interconnect
lines. Closed-form equations have been derived analytically for ground and coupling
capacitance. First, the capacitance model for a single line is developed, and then the new
model is used to derive expressions for the capacitance of a line surrounded by neighboring
lines in the same and the adjacent layers above and below. These expressions are simple, and
the calculated results are within 10% of Ansys Q3D extracted values.
Through silicon via (TSV) is one of the key components of the emerging 3D ICs.
However, increasing number of TSVs in smaller silicon area leads to some severe negative
impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of
the major challenges of 3D integration. In this paper, different materials for the cores of the
vias and the interposers are investigated to find the best possible combination that can reduce
crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored
glass and silicon as interposer materials. The simulation results indicate that glass is the best
option as interposer material although silicon interposer has some distinct advantages. For
via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From
the analysis it can concluded that W would be better for high frequency applications due to
lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal
expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be
in between Cu and W. However, W has a thermal expansion coefficient close to silicon.
Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for
high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission
coefficient and crosstalk in the vias.
Signal speed in current digital systems depends mainly on the delay of interconnects.
To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit
(vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to
ensure much smaller interconnect lengths, and lower delay and power consumption
compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit
performance depends on different electrical parameters (capacitance, resistance, inductance)
of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the
design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance,
resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived
from the physical shape and the size of the TSV. The modeling approach is comprehensive
and includes both the cylindrical and tapered TSVs as well as the bumps.
On-chip integration of inductors has always been very challenging. However, for sub-
14nm on-chip applications, large area overhead imposed by the on-chip capacitors and
inductors has become a more severe concern. To overcome this issue and ensure power
integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The
proposed TSV based inductor has the potential to achieve both high density and high
performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV
based inductor is also presented. The implementation of the VCO is intended to study the
feasibility, performance, and real-world application of the proposed TSV based inductor.
Title from PDF of title page viewed June 21, 2021; Dissertation advisor: Masud H. Chowdhury; Vita; Includes bibliographical references (pages 133-138); Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021
2021-01-01T00:00:00ZA Computational Study of The Electrical Response of Biological Cells with Realistic Three-Dimensional Morphologies
https://hdl.handle.net/10355/86708
A Computational Study of The Electrical Response of Biological Cells with Realistic Three-Dimensional Morphologies
Baidya, Somen
One of the unique features of a biological cell is the cell membrane that protects the cell interior by establishing a physical barrier between the cytoplasm and the extracellular matrix and governs the distribution of the cytoskeleton to control the three-dimensional (3D) morphology of a cell. From an electrical standpoint, the cell membrane represents an insulating layer with selective ion permeability, thereby administering an ionic imbalance between the conductive extracellular and intracellular fluids. Consequently, the electrical characterization of a biological cell mostly focuses on the specific electrical properties of the cell membrane and the means to modulate its semipermeable nature. Previously reported research studies had revealed many characteristics of the cell membrane. However, they did not explore the morphological feature to its fullest, especially in three dimensions. Motivated by this knowledge gap, this work explores the effect of the 3D variations in cell morphology on the electrical response of biological cells.
The most diverse and accurate 3D cell database developed to date by the National Institute of Standards and Technology was incorporated in this study, and an extensive investigation of these cells’ electrical characteristics was manifested by computational means. The cell database has hundreds of morphologies that were reconstructed from stem cells grown in different environments. To quantify how cell morphology affects the electrostatic properties of these complex cells, a validation study was conducted to study the polarizability tensors of stem cell morphologies, using three independent computational techniques. To draw accurate conclusions, the polarizability tensors of more than 1000 stem cells were calculated and statistical analysis was conducted to identify which growth environment generates cells with similar electric properties. Next, we studied the induced transmembrane voltage (ITV) across the cell membrane when it is subjected to a static and dynamic external electrical stimulus. The ITV generated across a cell’s membrane plays a significant role in the process of electroporation since the membrane permeability increases when the ITV exceeds a certain threshold. By setting an arbitrary ITV electroporation threshold, the electroporated area for each stem cell morphology at different orientations was calculated and significant differences were shown in comparison to spherical cells of similar size. The significance of morphological variation is more prominent for dynamic frequency-dependent excitation. Using computational experiments, it has been observed that as the frequency of the excitation increases, the ITV decreases beyond a certain cutoff frequency that varies with cell morphology.
While the ITV study is vital in low-frequency applications, the nonlinear membrane dynamics must be taken into consideration in case of high intensity ultra-short electrical stimulus, commonly used in supra-electroporation techniques to penetrate the internal organelles’ (i.e. nucleus, mitochondria, etc.) membrane. As a consecutive step of this research, a computational testbed was developed upon the stem cell geometries to investigate the supra-electroporation phenomenon in realistic cell shapes. The results obtained from this study suggest that supra-electroporation is highly dependent on the cell membrane irregularity, especially the location of the internal organelle with respect to any protrusion on the cell surface. The results from this observation can be utilized to engineer selective targeting of the desired cell with specific morphology.
Title from PDF of title page, viewed September 21, 2022; Dissertation advisor: Ahmed M. Hassan; Vita; Includes bibliogaphical references (pages 119-132); Dissertation (Ph.D)--Department of Computer Science and Electrical Engineering, Department of Physics and Astronomy. University of Missouri--Kansas City, 2021
2021-01-01T00:00:00ZA Hardware/Software Co-integration Approach for Securing Network
Infrastructure using Reconfigurable Computing
https://hdl.handle.net/10355/91461
A Hardware/Software Co-integration Approach for Securing Network
Infrastructure using Reconfigurable Computing
Danesh, Wafi
In the last two decades, there has been a rapid proliferation of connected devices spanning various application domains. Coupled with the rise of novel computer networking paradigms, such as Internet-of-Things (IoT), edge computing, fog computing, cloud computing among others, experts predicted an estimated 50 billion connected devices by the year 2020. The emergence of these networking paradigms, however, raises critical security vulnerabilities. Such vulnerabilities, as a result, exposes new attack vectors to exploitation by increasingly competent attackers, with ever more sophisticated means at their disposal, at both the software and hardware level.
The key reasons for the existence of such vulnerabilities in modern computer networks, arise due to the multifaceted constraints that need to be incorporated. Many current networking applications work under operating conditions of severe cost, power, and resource constraints. As a consequence of these constraints, the requisite computational resources required to incorporate critical security countermeasures are significantly reduced. Developers and system designers for the varied modern computer networking systems are often forced into a tradeoff of conventional security features, such as encryption, authentication, access control, network, and access security. At the software level, these vulnerabilities manifest in the form of unforeseen network intrusions, such as zero-day attacks. At the hardware level, a very serious threat are hardware Trojans (HT), which are clandestine, malicious circuits that can be inserted during runtime in the network infrastructure.
In this dissertation, two key security countermeasures are proposed against vulnerabilities at both the hardware and software levels. Based on these countermeasures, an attempt is made to synthesize both countermeasures and propose a unified security paradigm, which can tackle both threat scenarios simultaneously. At the hardware level, this dissertation focuses on the serious threat posed by hardware Trojan (HT) insertion in the field programmable gate array (FPGA) configuration bitstream. Low-end FPGAs are widely used in networking infrastructure and forego critical security features such as encryption of bitstreams to optimize resource constrained deployment. An attacker can reverse engineer the configuration bitstream to insert HTs, which are clandestine malicious circuits, in the FPGA. The proposed countermeasure uses bitstream reverse engineering to perform HT detection and is scalable to any circuit size and topology. With regards to the software level, this dissertation focuses on the vulnerability of deep learning (DL) based network intrusion detection to adversarial examples in IoT networks. Even though DL approaches have proven extremely effective in intrusion detection given the high volume of network traffic in modern IoT networks, DL models are prone to misclassification to minute perturbations in input samples, called adversarial examples. In this dissertation, an unsupervised adversarial example detection approach is proposed which does not require extra hardware overhead for implementation and is based on the intrinsic characteristics of the DL model implemented.
As an additional research focus, this dissertation investigates the use of multi-valued logic (MVL) in a circuit decomposition and synthesis approach for beyond Moore circuit implementations. MVL computing provides a larger information capacity compared to binary CMOS logic and is suitable for providing efficient data compression, processing, and communication with the massive network traffic volumes in modern computer networks. Some of the key issues preventing widespread adoption of MVL computing are the complex MVL expressions obtained from traditional logic decomposition approaches and the inefficient usage of binary switches for MVL data representation, communication, and processing. Therefore, this dissertation proposes a logic decomposition and synthesis algorithm for MVL, which combines concepts from machine learning and nanoelectronics. The proposed algorithm decomposes a MVL function to a set of linear expressions implemented by simple output summations, is adaptable to any device technology and radix of representation, and scalable with circuit size and topology. Compared to other popular MVL decomposition methods, the proposed algorithm presents significant savings in hardware overhead and computational complexity. In recent years, small but significant research efforts have been dedicated to usage of MVL in DL classifier design and HT detection. These innovations can pave the way for integrating MVL approaches in the security context at both the hardware and software level. In summary, this dissertation provides a detailed investigation of key security vulnerabilities at the software and hardware levels for modern computer networks, proposes adept and effective countermeasures and in addition, provides a proof-of-concept for a MVL decomposition and synthesis approach for beyond Moore circuits.
Title from PDF of title page, viewed September 14, 2022; Dissertation advisor: Mostafizur Rahman; Vita; Includes bibliographical references (pages 68-85); Dissertation (Ph.D)--Department of Computer Science and Electrical Engineering. University of Missouri--Kansas City, 2022
2022-01-01T00:00:00Z