Redundant adder architectures for cell-based technology

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Redundant adder architectures for cell-based technology

Please use this identifier to cite or link to this item: http://hdl.handle.net/10355/12412

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Title: Redundant adder architectures for cell-based technology
Author: Kharbash, Fekri Q.
Date: 2012-01-06
Publisher: University of Missouri--Kansas City
Abstract: The amenity of our daily lives has come to rely on an enormous number of embedded systems, such as mobile phones, anti-spin systems for cars, high de nition streaming video and portable devices. The utmost important operation used in these systems and digital system in general is addition, since it is a fundamental operation of most arithmetic operations. The choice of arithmetic numbering system for this operation, its digit set and its possible encoding in addition to algorithms and their hardware implementations has been subject to continual advancement to allow superior speed and to reduce digital circuit area and power consumptions. In the case of conventional number systems, addition speed is logarithmically bounded by the number of digits. However, unconventional number systems provide the possibility of performing the addition operation with sub-logarithmic and even constant latency. In this dissertation, we present the hardware-e cient addition rules for the unconventional binary signed digit number (BSDN) system to facilitate the BSDN adders design. We use the rules with the possible addition schemes and the two bits encodings to investigate and introduce new architectures. The implementation results of the existing and proposed structures show that each structure has its own performance gures based on the employed encoding. Moreover, it show that the hardware-e cient rules provide designs that demonstrate higher gures compared to existing designs when considering area, delay, power and combined performance measures. This work also presents the hardware design and performance analysis of a BSDN adder structure employing the 1-out-of-3 encoding. This encoding adds an error detection capability to the adder's architecture at di erent levels. The adder performance gures indicate that its bene t lies primarily on providing error detection features as it is slower, consumes more area and dissipate more power compared to designs employing the two-bits encoding. We also present the limited selective redundancy injection (LSRI) technique to introduce limited redundancy to conventional adders. The theoretical analysis and implementation results show that the conventional adders with LSRI outperform adders without LSRI in area, delay, power and combined performance measures where there is no strict requirement on accuracy
URI: http://hdl.handle.net/10355/12412

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