Device-level composition in ReWire

Abstract

[ACCESS RESTRICTED TO THE UNIVERSITY OF MISSOURI AT AUTHOR'S REQUEST.] ReWire provides engineers with a tool to specify, verify and implement hardware devices for FPGAs from a high-level Haskell-like language. Previous work has shown ReWire to be a productive source language for developing whole systems in the form of single, monolithic monadic specifications. To achieve scale, modularity and reusability, some form of modularity principle must be identified and realized within ReWire. What are the basic units of a ReWire specification and how may such units be identified, abstracted over and reused to achieve a realistic work flow for device construction in ReWire? This research identifies a modularity principle for ReWire as a suite of language abstractions for breaking apart ReWire specifications into its constituent components called Connect Logic and considers its implementation and application. Extending ReWire with support for device-level composition would significantly enhance its usefulness. This work integrates a suite of functions into ReWire which provide engineers the ability to incorporate existing specifications into new designs and the ability perform traditional decomposition of large specifications. Connect Logic provides an intuitive way to consider synchronous versus combinational logic in hardware designs. We demonstrate applications of Connect Logic to improve the performance of systems including cryptographic ciphers. We utilize Connect Logic to develop a fully pipelined microprocessor, to implement commonly used high-level concurrency primitives in hardware, and we demonstrate Connect Logic as a substrate for visual programming.