Effect of gate length in enhancing current in a silicon nanowire wrap around gate MOSFET

Abstract

[ACCESS RESTRICTED TO THE UNIVERSITY OF MISSOURI AT AUTHOR'S REQUEST.] A 3-D silicon nanowire wrap around gate (WAG) MOSFET was designed and it was shown that the properties of the cylindrical channel silicon nanowire device were inline with those of a conventional MOSFET. The concept of interferometric lithography was introduced for the fabrication of nanowire. The current conduction process through the nanowire device has been investigated. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The subthreshold slope characteristics were calculated for the nanowire device. Improvements in the nanowire WAG MOSFET has been investigated by changing nanowire device dimensions. The positive impact of reducing gate length on current along the channel of a silicon nanowire wrap-around-gate MOSFET has also been demonstrated. It has been shown analytically that in a WAG MOSFET with shorter gate length, transverse electric field in the channel is suppressed considerably which result in improved carrier mobility and drift velocity along the channel as compared to a WAG MOSFET with a longer gate length. Simulated I-V characteristics of short and long gate nanowire WAG MOSFETs have been presented and it has been found that for 50 nm channel diameter, the current in a short gate device is almost four times higher than that in a long gate device.