Nanoscale Nonvolatile Memory Circuit Design using Emerging Spin Transfer Torque Magnetic Random Access Memory
The spin transfer torque magnetic random access memory (STT-MRAM) is suitable for embedded and second level cache memories in the mobile CPUs. STT-MRAM is a highly potential nonvolatile memory (NVM) technology. There has been a growing demand to improve the efficiency and reliability of the NVM circuits and architectures. we present a modified STT MRAM cell design, where each cell is comprised of one magnetic tunneling junction (MTJ) device and a regular access transistor. We provide analysis of device, circuit and memory architecture level issues of STT-MRAM. The Modified 1M1T STT-MRAM bit cell circuit offers simpler and more area- and power- efficient design compared to the existing STT-MRAM cell design. Some device-circuit co-design issues are investigated to demonstrate ways to reduce delay in MRAM circuits based on MTJ. An 8x8 conventional MRAM array is implemented using the existing 2M2T cell and the Modified 1M1T cell to perform a comparative analysis at the architecture level. The non-volatile nature of the proposed STT-MRAM is verified through SPICE simulation. The circuit implementations and simulations are performed for 45nm technology node. As the transistor scales down it is prone to subthreshold leakage, gate-dielectric leakage, Short channel effect and drain induced barrier lowering. Now alternative of Access transistor is needed. We are using FinFET as access transistor in the STT-MRAM bit cell. FinFET based bit cell is designed to get an advantage of scaling down. Analysis is done and proven that the power consumption, standalone leakage current is less when compared to NMOS based STT-MRAM bit cell. Also determined FinFET based bit cell produces less access time to access the logic value from MTJ. Now, Industry is looking to have computational and storage capability together and that can be achieved through STT-MRAM. Addition to that there is a possibility to reduce power consumption and leakage more. So replacing FinFET technology with Carbon Nano Tube Field Effect Transistor (CNTFET) is required. As the conventional STT-MRAM requires certain current to reverse the magnetization of MTJ and one CNTFET alone cannot produce sufficient current required to store the logic value into MTJ. So new Bit cell is proposed using 3 CNTFET and 1 MTJ, this bit cell is capable of storing 3 logic values at a time that is capable of doing computation and act as AND gate. Also it utilizes less power to be in active region. Sensing of any memory system is one of the main challenge in industry to get better performance with less resources. Conventional Sense Amplifier (SA) used to sense the value from SRAM, DRAM memory system is also used to sense the STT-MRAM memory. But use of conventional SA is prone to some error. Modified Sense Amplifier is designed to overcome the error produced from the conventional SA. It is compared with all the existing SA to get the performance details of the modified SA.
Table of Contents
Introduction -- Planar NMOS based STT-MRAM bit cell analysis and circuit designing -- Performance improvement using FINFET based STT-MRAM circuit design -- Logic-in-memory using CNT-FET based STT-MRAM bit cell and optimization -- Error free sense amplifier design for STT-MRAM nonvolatile memory