MizzouSMP

Abstract

This paper covers the implementation of a 32 Bit RISC multiprocessor MizzouSMP. It was developed from MizzouRisc, simulated on Aldec Active HDL, implemented on a Altera DE2 board. The MizzouSMP core can be configured to contain one or more internal MizzouRisc cores. The cores of the multiprocessor have a reduced instruction set consisting of eleven instructions implemented by a controller with 25 states connected to a datapath with the time of execution of the instructions ranging from one to three cycles. Shared variables and memory area were added in order to facilitate communication between the cores. Testing consisted of two configurations: each core having a private ROM and all cores sharing a global ROM. An assembler was implemented in order to program in the MizzouRisc assembly language and a demonstration program was created. Upon measure the program completion time from one to ten cores for simulation and one to four cores for synthesis, MizzouSMP preformed as expected and predicted by Amdahl's law.