Design Automation and Evaluation Of Emerging 3D – IC Technology Using Stacked Horizontal Nanowires

Abstract

Miniaturization of integrated circuits (ICs) has continuously enabled advancement in modern technology. This miniaturization trend, also known as Moore’s law, needs to be maintained intact to meet the current day computational demands. Further miniaturization of transistors below sub 10nm regime now faces fundamental device scaling and interconnect bottlenecks. These limitations are alternatively addressed through 3-D integration of ICs, where pre-fabricated dies or wafers are stacked in a vertical manner. The existing 3-D ICs can be categorized into multilithic and monolithic 3-D integration approaches. However, both existing approaches provide only incremental density benefits, and face reliability, thermal management, large area vertical interconnects, and sequential fabrication challenges. To surpass these challenges, emerging 3-D IC approaches like transistor level Monolithic 3-D, Skybridge 3-D and Stacked Horizontal Nanowire 3-D (SN3D) have been actively pursued in research and show promising benefits. Our emerging 3-D IC approach is SN3D, where we envision to integrate circuits into a fabric of horizontally stacked nanowires. Our team has previously evaluated key requirements and manufacturing pathway for SN3D as well as designed logic and memory circuits. Nevertheless, any emerging 3-D IC approach has to find a pathway to fit into IC design phase based on Electronic Design Automation (EDA) tools before fabrication. In this thesis, we investigate the EDA tool-based design flow for SN3D and evaluate the SN3D circuits from fundamental cell level (standard cell level) to system level using industry standard EDA tools from Cadence Design Systems. A standard cell library containing three cells is designed and benchmarked with 2D CMOS. A system level flow is implemented for a large-scale arithmetic circuit and benchmarked with 2D CMOS. Our benchmarking results show 1.11x, 3.11x and 5.24x benefits in terms of power, performance and area with respect to 2D CMOS for a large-scale arithmetic circuit.