A novel approach to embedding memory with crosstalk logic circuits for high performance applications

Abstract

One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by data-intensive applications like artificial intelligence, cloud computing, and machine learning, we intend to integrate memory with the logic to get built-in memory logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed by the novel computing technique called Crosstalk Computing, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this work, we present how Crosstalk Computing can be leveraged to embed memory in logic. We have manifested the in-built memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed with the equivalent static CMOS circuits to compare the number of transistors, performance, and power. It is observed that the number of transistors consumed by the CBML logic circuits like 3-input AND, OR, is 40% less than the equivalent CMOS circuits. The cascaded CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters, etc.,) is up to 46% less, and performance is improved by 27% than the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. The qualitative analysis with the existing flip-flop architectures shows that the transistor count reduction of the CBML circuits is around 45% less than the architectures like Semi-dynamic Single-Phase Pulsed FF (SDFF), Dual dynamic node FF (DDFF) which embed logic into their flip-flop circuits. Additionally, these existing architectures do not have capability to embed complex circuits like full adder into a single flip-flop circuit. Hence, CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.